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STV9432TAP
100MHz OSD FOR MONITOR INCLUDING BEAM CURRENTS, VIDEO TIMING ANALYZER AND PWMs
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MULTIFUNCTION OSD FOR MONITOR INCLUDES FACILITIES FOR CUT-OFF VOLTAGE MONITORING: - THREE 8 BITS ADC INPUTS - ADC TRIGGER DURING RETRACE TIME OF A PROGRAMMED LINE INCLUDES FACILITIES FOR SCREEN SIZE & CENTERING AUTO SETUP - HS, VS, VIDEO TIMING MEASUREMENTS 100MHz MAX. PIXEL CLOCK, AVAILABLE FOR ANY LINE FREQUENCY BETWEEN 15 AND 140 kHz 12 x 18 CHARACTER ROM FONT INCLUDES: - 240 MONOCOLOR CHARACTERS - 16 MULTICOLOR CHARACTERS CHARACTER FLASHING UP TO 1K CHARACTERS TEXT DISPLAY ULTRA HIGH FREQUENCY PLL FOR JITTER-FREE DISPLAY FLEXIBLE DISPLAY: - ANY CHARACTER WIDTH AND HEIGHT - ANYWHERE IN THE SCREEN SINGLE BYTE CHARACTER CODES AND COLOR LOOK-UP TABLE FOR EASY PROGRAMMING AND FAST ACCESS CHARACTER FLIP OPERATIONS WIDE DISPLAY WINDOW ALLOWS PATTERN GENERATION FOR FACTORY ADJUSTMENTS I2C BUS MCU INTERFACE FIVE 8 BITS PWM DAC OUTPUTS
ating at very high frequency, gives an accurrate display without visible jitter for a wide line frequency range from 15 to 140 kHz. - Cut-off Monitoring Circuitry includes: 5 x 8 bits PWM DACs, 3 x 8 bits ADCs and a programmable ADC sampling trigger. It gives the possibility to measure the three beam currents, during the horizontal flyback, at a given line in the frame, provided that the three ADC inputs are connected to a beam current sensing circuitry. The values are stored in three BEAM CURRENT REGISTERS, and available for MCU read. - Video Timing Analyzer. Using the Horizontal Sync, Vertical Sync, Horizontal Flyback, and "Video Active" inputs, a set of counters give the different timing measurements necessary to analyze the current Video timing characteristics in order to make the automatic set-up of screen size and centering. The measurements are initialized on the same programmable trigger line than in the above cut-off monitoring circuitry.
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SO28 (Plastic Micropackage) ORDER CODE: STV9432TAP
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DESCRIPTION
Connected to a host MCU via its serial I2C Bus, the STV9432TAP is a multifunction slave peripheral device integrating the following blocks: - On-screen Display. It includes a MASK PROGRAMMABLE ROM that holds the CUSTOM CHARACTER FONT, a 1Kbytes RAM that stores the code strings of the different lines of text to be displayed, and a set of registers to program character sizes and colors. A built-in digital PLL, oper-
Version 4.0
February 2000
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
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STV9432TAP
1 - PIN CONNECTIONS
FILTER AGND SDA SCL HS VS HFLY AV DVDD DVSS/OVSS XTI XTO PWM1 PWM2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TEST ADCREF RCI GCI BCI AVDD OVDD FBLK BOUT GOUT ROUT PWM5 PWM4 PWM3
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STV9432TAP
2 - PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol FILTER AGND SDA SCL HS VS HFLY AV DVDD DV SS/OVSS XTI XTO PWM1 PWM2 PWM3 PWM4 PWM5 ROUT GOUT BOUT FBLK OVDD AVDD BCI GCI RCI ADCREF TEST Type I/O Power I/O I I I I I Power Power I O O O O O O O O O O Power Power I I I I/O I/O PLL Filter Analog Ground I2C Bus Serial Data I2C Bus Serial Clock Horizontal Sync Input Vertical Sync Input Horizontal Flyback Input Active Video Input Digital +5V Power Supply Digital and RGB Output Ground Crystal Oscillator Input Crystal Oscillator Output PWM DAC Output 1 PWM DAC Output 2 PWM DAC Output 3 PWM DAC Output 4 PWM DAC Output 5 Red Output Green Output Blue Output Fast Blanking Output +5V Supply for the RGB Outputs Analog +5V Power Supply Blue Beam Current Input Green Beam Current Input Red Beam Current Input ADC Reference Voltage Pin Pin to be connected to ground Description
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3 - BLOCK DIAGRAM
13 14 XTI XTO 11 OSCILLATOR 12 8 BITS PWMs 15 16 17 FILTER 1 PLL 22 18 HFLY VS 7 6 DISPLAY 19 CONTROLLER 20 TIMINGS ANALYZER 1k BYTES RAM 10 BEAM CURRENT MEASUREMENT CHARACTER FONT ROM 2 21
PWM1 PWM2 PWM3 PWM4 PWM5 OV DD ROUT GOUT BOUT FBLK
HS AV
5 8
DV SS/OVSS AGND
RCI 26 GCI 25
BCI 24 ADCREF 27 AVDD 23 9
I2C BUS INTERFACE 3.3V VOLTAGE REGULATOR
3 4 28
SDA SCL TEST
DV DD
POWER-ON RESET
STV9432TAP
4 - ABSOLUTE MAXIMUM RATINGS
Symbol AVDD, DV DD, OVDD VIN Toper Tstg Supply Voltage Input Voltage Operating Temperature Storage Temperature Parameter Value -0.3, +6.0 VSS-0.3, VDD+0.3 0, +70 -40, +125 Unit V V
o o
C C
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5 - ELECTRICAL CHARACTERISTICS
(VDD = 5V, VSS = 0V, GND = 0V, T A = 0 to 70o, unless otherwise specified)
Symbol
SUPPLY
Parameter
Supply Voltage Analog and Digital Supply Current
Min. 4.75 -
Typ. 5 -
Max. 5.25 150 0.8
Unit V mA V V A V V
AVDD, DV DD, OVDD AIDD+ DI DD + OIDD INPUTS (SCL, SDA) VIL VIH IIL VIL VIH VHYST IPU HSIN V OL V OL VOH IIL I IH VIL VIH V OL VOH ADCREF VREF V OL VOH t PWM POWER-ON RESET DV DDTH VIN Z IN VOFF ILEAK ILE DLE
Input Low Voltage Input High Voltage Input Leakage Current
2.4 -1 +1 0.8
HS, VS, AV HFLY
INPUTS (HS, VS, AV, HFLY)
Input Low Voltage Input High Voltage
2.4 3.6 0.4 100 15 0 0 0.8V DD 3 3 0.7V DD 0 0.8V DD 3.3 0 VCC - 0.5 256 3.6 0 100 3 0 -2 -0.5 50 +2 +0.5 VADCREF 0.4 0.4 VDD 140 0.4 0.4 VDD 15 15 1.4
Schmidt Trigger Hysteresis Pull-up Source Current (VIN = 0V) Horinzontal Synchro Input Range
V A kHz V V V A A V V V V V V V tOSC V V k LSB
OUTPUTS (SDA open drain)
Output Low Voltage (IOL = 3mA) Output Low Voltage (IOL = 3mA) Output High Voltage (IOH = 3mA) XTI Input Source Current (VIN = 0V) XTI Input Sink Current (VIN = VDD) XTI Input Low Voltage XTI Input High Voltage XTI Output Low Voltage (IOL = 3mA) XTI Output High Voltage (IOH = 3mA) Output Voltage Reference
OUTPUTS (R, G, B, FBLK)
OSCILLATOR (XTI, XTO)
8 BITS PWM DACs 1,2,3,4,5
Output Low Voltage (IOL = 1.6mA) Output High Voltage (IOH = -0.8mA) PWM Period
Supply Threshold Level
8 BITS ADC INPUTS (RCI, GCI, BCI)
Input Voltage Input Impedance Input Offset Voltage Input Leakage Current Integral Linearity Error (Note 2) Differential Linearity Error (Note 2)
A
LSB LSB
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STV9432TAP
6 - TIMINGS
Symbol OSCILLATOR fOSC fPXL tR tF tSKEW fSCL tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tF tR
ANALYZER (HS, HFLY, AV) Clock Frequency Maximum Pixel Frequency Rise Time (see Note 1) Fall Time (see Note 1) Skew between R, G, B, FBLK SCL Clock Frequency Time the bus must be free between 2 access Hold Time for Start Condition Set up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set up Time Data Fall Time of SDA Rise Time of both SCL and SDA
Parameter
Min.
Typ. 8
Max.
Unit MHz
100 5 5 5 0 500 500 500 400 400 0 500 20 400
MHz ns ns ns kHz ns ns ns ns ns ns ns ns
R, G, B, FBLK (CLOAD = 30pF)
I2C INTERFACE: SDA AND SCL (see Figure 1)
Depend on the pull-up resistor and the load capacitance 2 2 4091 4091 Hfly 2 2 4091 4091 Lines Lines tHTIM tHTIM
tHLOW tHHIGH Hs
ANALYZER (VS)
Low Pulse Width (see Note 3) High Pulse Width Hs Frequency Low Pulse Width High Pulse Width
tVLOW tVHIGH
Notes: - These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches coming from corners of our processes and also temperature characterization. - The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal devices. - tHTIM = 3tOSC : 40.
Figure 1.
STOP START tBUF SDA tHDS SCL tHIGH tLOW tSUDAT tSUP DATA tHDAT STOP
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7 - SERIAL INTERFACE
The 2-wires serial interface is an I2C interface. To be connected to the I2C bus, a device must own its slave address; the slave address of the STV9432TAP is BA (in hexadecimal).
A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 RW
- The successive bytes of data. All bytes are sent MSB bit first and the write data transfer is closed by a stop.
7.2 - Data Transfer in Read Mode
The host MCU can read data from the STV9432TAP register, RAM or ROM. To read data from the STV9432TAP (Figure 3), the MCU must send 2 different I2C sequences. The first one is made of I2C slave address byte with R/W bit at low level and the 2 internal address bytes. The second one is made of I2C slave address byte with R/W bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence.
7.1 - Data Transfer in Write Mode
The host MCU can write data into the STV9432TAP registers or RAM. To write data into the STV9432TAP, after a start, the MCU must send (Figure 2): slave byte with a low level for - First, the R/W bit, - The two bytes of the internal address where the MCU wants to write data, the I2C address
Figure 2. I2C Write Operation
SCL R/W SDA Start I2 C Slave Address ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK A13 A12 A11 A10 A9 A8 ACK
LSB Address
MSB Address
SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
Data Byte 1
Data Byte 2
Data Byte n
Figure 3. I2C Read Operation
SCL
R/W SDA Start I C Slave Address
2
A7
ACK
A6
A5
A4
A3
A2
A1
A0 ACK
-
-
A13 A12 A10 A10 MSB Address
A9
A8 ACK Stop
LSB Address
SCL
SDA Start I2C Slave Address
R/W
ACK*
D7
D6
D5
D4
D3
D2
D1
D0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK Stop
Data Byte 1
Data Byte n
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7.3 - ADDRESSING SPACE 7.3.1 - General Mapping
STV9432TAP registers, RAM and ROM are mapped in a 32Kbytes addressing space. The mapping is the following:
0000 03FF 0400 07FF 0800 3FFF 4000 403F 4040 7FFF 1024 bytes RAM Empty Space Character Generator ROM Internal Registers Empty Space
Descriptors and character codes
Important Notice: All 16 bits datas are mapped LSB byte at lower address and MSB byte at higher address. - Example: H1 12 bits register: @4000: 8 LSB bits - @4001: 4 MSB bits. - Descriptors must also be written to RAM LSB byte first.
7.3.2 - I2C Registers Mapping
4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E 400F 4010 4011 4012 4013 4014 4015 4016 4017-401F 4020 4021 4022 4023 H1 LSB H1 MSB H2 LSB H2 MSB H3 LSB H3 MSB H4 LSB H4 MSB H5 LSB H5 MSB H6 LSB H6 MSB V1 LSB V1 MSB V2 LSB V2 MSB V3 LSB V3 MSB RCI GCI BCI SBN TIMG Reserved Color 0 Color 1 Color 2 Color 3 4024 4025 4026 4027 4028 4029 402A 402B 402C 402D 402E 402F 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 403A 403B 403C 403D-403E 403F 4040-7FFF Color 4 Color 5 Color 6 Color 7 Color 8 Color 9 Color 10 Color 11 Color 12 Color 13 Color 14 Color 15 Line Duration Top Margin Horizontal Delay Character Height Display Control Locking Time Constant Capture Time Constant Initial Pixel Period PWM1 PWM2 PWM3 PWM4 PWM5 Reserved RST Reserved
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8 - TIMING ANALYZER
8.1 - VIDEO HORIZONTAL TIMINGS
All horizontal timing measurements use a 106.7MHz clock. This clock is made from the internal oscillator: fHTIM = 40fOSC : 3. These twelve bits read-only registers read time measurements, given in t HTIM units. They hold the value of the last measurement that was initiated by I2C command (see TIMG Register).
Figure 4.
AV HS HFLY E
C
A D F
B C' E' D' F'
A'
H1 Register: H sync to Active video, min of C to A
4000 4001 H1.7 H1.6 H1.5 H1.4 H1.3 H1.11 H1.2 H1.10 H1.1 H1.9 H1.0 H1.8
H2 Register: Active video to H sync, min of B to C'
4002 4003 H2.7 H2.6 H2.5 H2.4 H2.3 H2.11 H2.2 H2.10 H2.1 H2.9 H2.0 H2.8
H3 Register: Line period, C to C'
4004 4005 H3.7 H3.6 H3.5 H3.4 H3.3 H3.11 H3.2 H3.10 H3.1 H3.9 H3.0 H3.8
H4 Register: H Fly to H sync, E to C
4006 4007 H4.7 H4.6 H4.5 H4.4 H4.3 H4.11 H4.2 H4.10 H4.1 H4.9 H4.0 H4.8
H5 Register: H sync to H Fly, C to E'
4008 4009 H5.7 H5.6 H5.5 H5.4 H5.3 H5.11 H5.2 H5.10 H5.1 H5.9 H5.0 H5.8
H6 Register: H fly pulse, E to F
400A 400B H6.7 H6.6 H6.5 H6.4 H6.3 H6.11 H6.2 H6.10 H6.1 H6.9 H6.0 H6.8
8.2 - VIDEO VERTICAL TIMINGS
These twelve bits read-only registers read time measurements, given in number of scan lines. They hold the value of the last measurement that was initiated by I2C command (see TIMG Register).
Figure 5.
AV VS K A L B K' L' A'
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STV9432TAP
V1 Register: V sync to Active video, min. of K to A
400C 400D V1.7 V1.6 V1.5 V1.4 V1.3 V1.11 V1.2 V1.10 V1.1 V1.9 V1.0 V1.8
V2 Register: Active video to V sync, min. of B to K'
400E 400F V2.7 V2.6 V2.5 V2.4 V2.3 V2.11 V2.2 V2.10 V2.1 V2.9 V2.0 V2.8
V3 Register: Number of lines per frame, K to K'
4010 4011 V3.7 V3.6 V3.5 V3.4 -
'
V3.3 V3.11 V3.2 V3.10 V3.1 V3.9 V3.0 V3.8
8.3 - TIMING ANALYSIS TRIGGER
The Timing Analysis is performed according to the setting of SBN and TIMG registers:
8.3.1 - SBN Register
This 8 bits register holds the "sampling bloc" number. The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or Beam currents. The reset value of this register is 0.
4015 SBN7 SBN6 SBN5 SBN4 SBN3 SBN2 SBN1 SBN0
8.3.2 - TIMG Register
4016 STM NFR1 NFR0 ADCDLY3 ADCDLY2 ADCDLY1 ADCDLY0 SELECT
This 8 bits register holds the following parameters: STM : Start Measurement Bit. This bit has to be forced to 1 by I2C to start the measurement sequence, depending on the measurement selection bit. When measurement is completed the IC will reset this bit to 0. NFR number of measurement frames, 1 to 4 frames Cut-off Beam current ADC sampling delay time: 0 to 15 x tOSC , by tOSC steps Selection of Beam current measurement (0) or Timing measurement (1)
NFR [1:0] ADCDLY[3:0] SELECT
: : :
To initiate a Timing Analysis cycle: - program the Sampling Bloc Number in the SBN Register, - program the TIMG Register, with: "SELECT" bit =1, "NFR" bits specify the number of measurement frames (H1, H2, V1, V2), "STM" bit = 1 (Start Measurement). As soon as the measurement cycle is finished, the "STM" bit is automatically reset by the device. After a Timing Analysis cycle, reading a zero in STM bit of TIMG register means that the measurement is completed and the mcu may read the results in Hi and Vi registers.
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Figure 6. Video Timing Measurement sequence - "Select bit = 1" (TIMG register, bit 0)
I2C SET STM BIT (TIMG register)
WAIT FOR ACKNOWLEDGE BIT
WAIT FOR RISING EDGE OF VS
MEASURES H1 AT EVERY LINE DURING NFR+1 FRAMES. AFTER NFR+1 FRAMES, H1 HOLDS THE MIN.VALUE
MEASURES V3 WAIT FOR 4*SBN RISING EDGES OF HS
MEASURES V1 DURING NFR+1 AND KEEPS THE MIN. VALUE MEASURES H2 AT EVERY LINE DURING NFR+1 FRAMES. AFTER NFR+1 FRAMES, H2 HOLDS THE MIN.VALUE
ACQUISITION OF H3, H4, H5, H6
MEASURES V2 DURING NFR+1 AND KEEPS THE MIN. VALUE
AFTER NFR+1 FRAMES, RESET STM BIT
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STV9432TAP
9 - BEAM CURRENTS MEASUREMENT
9.1 - BEAM CURRENT MEASUREMENT REGISTERS The Beam Current Measurement circuitry uses three A to D converters, sampled at fOSC frequency. These three 8 bits registers read the values of the last Beam currents measurement, initiated by I2C command (see TIMG register). RCI Register: Red Beam Current Input
4012 RCI7 RCI6 RCI5 RCII4 RCI3 RCI2 RCI1 RCI0
GCI Register: Green Beam Current Input
4013 GCI7 GCI6 GCI5 GCI4 GCI3 GCI2 GCI1 GCI0
BCI Register: Blue Beam Current Input
4014 BCI7 BCI6 BCI5 BCI4 BCI3 BCI2 BCI1 BCI0
9.2 - BEAM CURRENT MEASUREMENT TRIGGER The Beam Currents Measurement is performed according to the setting of SBN and TIMG registers : 9.2.1 - SBN Register This 8 bits register holds the "sampling bloc" number. The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or Beam currents. The reset value of this register is 0.
4015 SBN7 SBN6 SBN5 SBN4 SBN3 SBN2 SBN1 SBN0
9.2.2 - TIMG Register
4016 STM NFR1 NFR0 ADCDLY3 ADCDLY2 ADCDLY1 0 SELECT
This 8 bits register holds the following parameters: STM : Start Measurement Bit. This bit has to be forced to 1 by I2C to start the measurement sequence, depending on the measurement selection bit. When measurement is completed the IC will reset this bit to 0. : NFR number of measurement frames, 1 to 4 frames
NFR [1:0]
ADCDLY : Cut-off Beam current ADC sampling [3:0] delay time: 0 to 15 x tOSC, by tOSC steps SELECT : Selection of Beam current measurement (0) or Timing measurement (1)
When measurement is completed the IC will reset this bit to 0. The reset value of this register is 0. To initiate a Beam Currents Measurement cycle: - program the Sampling Bloc Number in the SBN Register, - program the TIMG Register, with: "SELECT" bit = 0, "ADCDLY" bits specify the sampling time during HFly, "STM" bit = 1 (Start Measurement). As soon as the measurement cycle is finished, the "STM" bit is automatically reset by the device. After a Beam Currents Measurement cycle, reading a zero in STM bit of TIMG register means that the measurement is completed and the MCU may read the results in RCI, GCI, and BCI registers.
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STV9432TAP
Figure 7. Beam Currents Measurement Sequence - "Select bit = 0" (TIMG register, bit 0)
I2C SET STM BIT (TIMG register)
WAIT FOR ACKNOWLEDGE BIT
WAIT FOR RISING EDGE OF VS
WAIT FOR 4*SBN RISING EDGES OF HS
WAIT FOR RISING EDGE OF HFLY
WAIT FOR ADC DLY
ACQUISITION OF RBC, GBC, BBC
RESET STM BIT
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10 - DIGITAL TO ANALOG PWM OUTPUTS
The five to A outputs PWM1 toc5 of the STV9432TAP are pulse width modulator type converter outputs. The frequency of the output signal is fOSC: 256 and the duty cycle is: Value [7:0]: 256. After an external low pass filter, the voltage value of the output is: Value [7:0] x VDD : 256. Figure 8.
PWM1 Signal
V1[7:0] 0 tOSC 1
256 x tOSC
128 255
10.1 - PWM REGISTERS
Pulse Width Modulator 1
4038 V17 V16 V15 V14 V13 V12 V11 V10
V1[7:0] : Digital value of the 1st PWM D to A converter (Pin 13) Pulse Width Modulator 2
4039 V27 V26 V25 V24 V23 V22 V21 V20
V2[7:0] : Digital value of the 2nd PWM D to A converter (Pin 14) Pulse Width Modulator 3
403A V37 V36 V35 V34 V33 V32 V31 V30
V3[7:0] : Digital value of the 3rd PWM D to A converter (Pin 15) Pulse Width Modulator 4
403B V47 V46 V45 V44 V43 V42 V41 V40
V4[7:0] : Digital value of the 4th PWM D to A converter (Pin 16) Pulse Width Modulator 5
403C V57 V56 V55 V54 V53 V52 V51 V50
V5[7:0] : Digital value of the 5th PWM D to A converter (Pin 17)
Note: Power-on reset default value of PWM register is OOH.
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STV9432TAP
11 - SOFTWARE RESET REGISTER
403F RST
To perform a software I2C reset of the device, set the RST bit to ONE. This bit will be automatically reset by the device. Software Reset will put all Write registers at their default power-on value, and reset all internal logic blocks except the I2C bus interface itself. It will not change the RAM contents.
12 - ON-SCREEN DISPLAY
The STV9432TAP on-screen display is able to display any line of characters (character strip) anywhere in the screen. Character strings are programmed by the MCU in RAM via I 2C bus. Character shapes are coded in the internal ROM font. Character strips may be 12.1 - RAM PROGRAMMING In the example shown in Figure 9, the OSD screen, is made of 9 strips. In RAM, there is: - one list of 9 Strip descriptors (size = 9 x 2 bytes = 18 bytes), - 6 Text strings, each of them is made of the character codes of the line of text. Text strings can be programmed anywhere in RAM. The Descriptor list can be located at 16 different addresses in RAM, this address is defined in the Display Control Register. It is consequently possible to store up to 16 different pages in RAM. The current Displayed page is specified in the Display Control Register. It refers to a given Page Descriptor list. Figure 9. Display Page: list of Character and Spacing strips
TOP MARGIN
adjacent or separated by vertical spaces (Spacing strips) Consequently, one display page is made of a list of Character strips and Spacing strips. A Top Margin and a Left Margin are programmable in dedicated registers.
12.1.1 - Two kinds of Data Strip Descriptors and Character Codes An OSD screen is made of a number of Character and Spacing strips. There are two groups of Data that make one OSD screen: - a Strip Descriptors list, - Text strings - one per Character strip. Each Strip is associated with a 2 bytes Strip Descriptor. There are two kinds of Strip Descriptors: - Character Strip Descriptors: they contain the Text string Ram address of the Character Strip, - Spacing Strip Descriptors: they specify the vertical space height.
Text line number one Text line number two
Strip 1 : Character Strip Strip 2 : Character Strip Strip 3 : Spacing Strip
LEFT MARGIN
Text line number three
Strip 4 : Character Strip Strip 5 : Spacing Strip
Text line number four Text line number five Text line number six
Strip 6 : Character Strip Strip 7 : Character Strip Strip 8 : Character Strip Strip 9 : Spacing Strip (Bottom Margin)
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12.1.2 - Descriptors Spacing
MSB LSB 0 SL7 L/ C SL6 SL5 SL4 SL3 SL2 SL1 SL0
L/ C
: LINE or CHARACTER spacing: = 0, spacing descriptor defined as character height (SL[7:0] = 1 to 255 character). = 1, spacing descriptor defined as scan line height (SL[7:0] = 1 to 255 scan lines). : Number of selected height (character or scan lines according L/ C ).
SL[7:0]
Character
MSB LSB
1 C7
DE C6
CLU3 C5
CLU2 C4
CLU1 C3
CLU0 C2
C9 C1
C8 C0
DE
: Display enable: = 0, R = G = B = 0 and FBLK = FBK bit of display control register on the whole strip, = 1, display of the characters. : Active color selection at the begining of the strip. : Address of the first character code of the strip. : Address 0 must be 0.
CLU[3:0] C[9:1] C0
12.1.3 - Code Format There are basically 3 kinds of code:
- the control codes from 0 to 15 (00H to 0FH), - the ROM monochrome character codes from 16 to 255 (10H to FFH), - the two bytes multicolor character codes from 08F0 to 08FF (Hex).
For code definitions see Table 1. Table 1 Character and Command Codes
0 1 2 3 4 5 6 7 0 col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 1 2 3 4 5 6 7 8 9 A B C D E F
240 Monochrome Characters
8 multicol 9 nop A vflip B hflip C dflip D call E rtn F eof Single byte codes 00 to 0f are command codes. Single byte codes 10 to ff are monochrome character codes. Double byte codes 08F0 to 08FF are multicolor character codes.
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Figure 10. Character Font for the STV9432TAP
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Control Codes Control codes must be followed by a displayable code, except for RTN & EOL. They must not be used twice consecutively without a displayable code between them. The control code CALL is preceded by an address byte. The control codes are not displayed except if mentioned. Codes 0 to 7 (0h to 7h): COL0 to COL7 codes select 1 byte among 8 within the CLUT in RAM. The block selection is fixed by CLU3 bit of the active character descriptor (see Table 1 and Table 2). Code 8 (08h): Multicolor character precode, must be followed by a multicolor character number from F0h to FFh. Code 9 (09h): NOP: no operation is performed, can be used to spare a location in RAM for an active control code. Codes 10 to 12 (0Ah to 0Ch): FLIPS: HFLIP(0Bh) Horizontal Flip code flips horizontaly the following displayable code. VFLIP(0Ah) Vertical Flip code flips verticaly the following displayable code. DFLIP(0Ch) Horizontal & Vertical Flip code flips horizontaly and verticaly the following displayable code. Code 13 (0Dh): CALL, this control code switch the display of the next character to the code address given by the next byte as following:
CALL CODE (odd @) MSB ADDRESS BYTE (even @) LSB 0 0 0 0 1 1 0 1
Code 14 (0Eh): RTN: return to the CALL + 1 code location (see Note). Code 15 (0Fh): EOL, end of line terminates the display of the current row. ROM Character Codes Codes 16 to 255 (10h to FFh): ROM monochrome character codes. The characters shapes are 12x18 pixel matrix described in Figure 11. Codes 256 to 272 (F0h to FFh): ROM multicolor character codes. They must be preceded by the multicolor pre-code 08h. The characters shapes are 12x18 pixel matrix described in Figure 11. 12.1.4 - OSD Look-up Table Color look-up table [CLUT] is read/write RAM table. Mapping address is described above in the section ROM Character Codes. The CLUT is splitted in 2 blocks of 8 bytes. Each byte contains foreground and background informations as described below:
TRA BR BG : : : : BB FL FR FG FB TRA FL BR, BG, BB FR, FG, FB Transparent background Flashing foreground Background color Foreground color
A8 A7 A6 A5 A4 A3 A2 A1
A[9:1]
: Address of the next code to be used (A0 = 0 only even addresses), in low half part of RAM.
Notes: CALL and RTN code must be used simultaneously. CALL and RTN codes are displayed as a SPACE character. CALL and RTN codes must be placed at odd addresses. They may be preceed by a NOP in order to place them at the right position.
Each block may store a different set of colors. One block of colors may be used for the normal items of the menu while the second block, with brighter colors, may be used for selected items of the menu. The block selection is done by programming bit CLU3 of CLU[3:0] of the character descriptor (see Table 2). It remains selected all the row long. Bit CLU2, CLU1 and CLU0 of CLU[3:0] of the character descriptor select the active color at the beginning of the row. The active color can be changed along the row, using 8 control codes COL0 to COL7. Each control code (COL0 to COL7) activate a dedicated color byte in the CLUT as described in Table 2.
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Table 2
CLU3
CLUT Block Selection
CLU[2:0] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Code Name Col Col Col Col Col Col Col Col Col Col Col Col Col Col Col Col 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Command Code (hex) 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 Ram @(hex) @4020 @4021 @4022 @4023 @4024 @4025 @4026 @4027 @4028 @4029 @402A @402B @402C @402D @402E @402F Reset Value (hex) 07 16 25 34 43 52 61 70 70 61 52 43 34 25 16 07
0
1
12.2 - OSD CONTROL REGISTERS
Line Duration (reset value: 20H)
4030 VSP HSP LD6 LD5 LD4 LD3 LD2 LD1
VSP
:
V-SYNC active edge selection = 0, falling egde, = 1, rising edge. HFLY active edge selection = 0, rising egde, = 1, falling edge. LINE DURATION LD0 = 0 LD1 = 2 periods of character One character period is 12 pixels long.
HSP
:
LD[6:1]
:
Top Margin (reset value: 30H)
4031 M[9:2] M9 M8 M7 M6 M5 M4 M3 M2
: TOP MARGIN height from the VSYNC reference edge. M0 = 0, M1 = 0 M2 = 4 scan lines
Note: The top margin is displayed before the first strip of descriptor list. It can be black if FBK of DISPLAY CONTROL register is set or transparent if FBK is clear.
Horizontal Delay (reset value: 20H)
4032 DD[7:0] DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 : HORIZONTAL DISPLAY DELAY from the HSYNC reference edge to the 1st pixel position of the character strips. Unit = 6 pixel periods. Minimum value is 08H. First pixel position = [DD[7:0] - 6] x 6 + 54 with DD[7:0] = 0,2,4,6 delay is 54 pixel and with DD[7:0] = 1,3,5 delay is 60 pixel
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Character Height (reset value: 24H)
4033
CH[5:0] :
-
-
CH5
CH4
CH3
CH2
CH1
CH0
HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is given by: SLICE-NUMBER = ( SCAN-LINE-NUMBER x 18 )
round
CH[5:0] SCAN-LINE-NUMBER = Number of the current scan line of the strip.
Display Control (reset Value: 00H)
4034 OSD FBK : : OSD FBK FL1 FL0 P9 P8 P7 P6
FL[1:0]
:
ON/OFF (if 0, R, G, B and FBLK outputs are 0). Fast blanking control: = 1, forces FBLK pin at "1" outside and inside the OSD area. This leads to blank video RGB and to only display OSD RGB. = 0, FBLK pin is driven according character code for normal display of OSD data. Flashing mode : - 00: No flashing. The character attribute is ignored, - 01: Flashing at fF (50% duty cycle), - 10: Flashing at 2 fF - 11: Flashing at 4 fF Note: fF is 128 time vertical frequency.
P[9:6]
:
Address of the 1st descriptor of the current displayed pages. P[13:10] and P[5:0] = 0; up to 16 different pages can be stored in the RAM.
FR AS2 AS1 AS0 LUK BS2 BS1 BS0
Locking Condition Time Constant (reset value: 01H)
4035
FR AS[2:0] BS[2:0] LUK
: : : :
Free Running; if = 1 PLL is disabled and the pixel frequency keeps its last value. Phase constant during locking conditions. Frequency constant during locking conditions. Lock unlock status bit 0 = unlocked PLL 1 = Locked PLL
Capture Process Time Constant (reset value: 24H)
4036 LEN AF2 AF1 AF0 BF2 BF1 BF0
LEN
AF[2:0] BF[2:0]
: Lock enable 0 = R,G,B, FBLK are always enabled, 1 = R,G,B,, FBLK are enabled only when PLL is locked. : Phase constant during the capture process. : Frequency constant during the capture process.
Initial Pixel Period (reset value: 06H)
4037 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PP[7:0]
: Value to initialize the pixel period of the PLL.
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12.3 - OSD TIMINGS The number of pixel periods is given by the LINE DURATION register and is equal to: [LD[6:1] x 2 + 1 ] x 12. (LD[6:1]: value of the LINE DURATION register). This value allows to define the horizontal size of the characters. The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to: (DD[7:0] -6) x 6 + 54 (DD[7:0]: value of the DISPLAY DELAY register). This value allows to define the horizontal position of the characters on the screen. Due to internal logic, minimum horizontal delay is fixed at 4.5 characters (54 pixel) when DD is even and lower or equal to 6, and it is fixed at 5 characters (60 pixel) when DD is odd and lower or equal to 7. 12.4 - PLL The PLL function of the STV9432TAP provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the R, G, B and fast blanking signals. It is made of 2 PLLs. The first one analog (see Figure 11) provides a high frequency that is 40 times the internal oscillator frequency, or 320MHz. This high frequency clock is used by the Display controller. The 320MHz frequency is then divided by three. The resulting 106.7MHz clock is used by the Video timings analysis block. The second PLL, full digital (see Figure 12), provides a pixel frequency locked on the horizontal synchro signal. The ratio between the frequencies of these 2 signals is: M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the value of the LINE DURATION register. Figure 11. Analog PLL
N * fOSC VCO 40 FILTER fOSC
12.4.1 - Programming of the PLL Registers Initial Pixel Period (@4037) This register allows to increase the speed of the convergence of the PLL when the horizontal frequency changes (new graphic standard). The relationship between PP[7:0], LD[6:1], fHSYNC and fOSC is: (
PP[7:0] = round 40 . f OSC 6 . (2 LD + 1) fHSYNC
. .
)
Figure 12. Digital PLL
M * fH-SYNC 40 *f OSC %D D(n) %M ALGO err(n) fH-SYNC
Locking Condition Time Constant (@ 4035) This register provides the AS[2:0] and BS[2:0] constants used by the algo part of the PLL (see Figure 11). These two constants as well as the phase error err(n) give the new value D(n) of the high frequency signal division. AS[2:0] and BS[2:0] fix the pixel clock frequency. These two constants are used only in locking condition, if the phase error is inferior to a fixed value during at least 4 scan lines. If the phase error becomes greater than this fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL used the other constants, AF[2:0] and BF[2:0], given by the next register. Capture Process Time Constant (@ 4036) The choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the PLL. 12.4.2 - How to choose the time constant value The time response of the PLL is given by its characteristic equation which is: (x - 1)2 + ( + ) . (x - 1) + = 0 Where: = 3 LD [6:1] . 2A -11 and = 3 . LD[6:1] . 2B - 19 (LD[6:1] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As you can see, the solution depends only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. If ( + )2 - 4 0 and 2 - < 4, the PLL is stable and its response is like that presented in Figure 14. If ( + )2 - 4 0 , the response of the PLL is like that presented in Figure 15. In this case the PLL is stable if > 0.7 damping coefficient). Table 3 gives some good values for A and B constants for different values of the LINE DURATION.
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STV9432TAP
Figure 13. Time Response of the PLL/ Characteristic equation solutions (with real solutions)
PLL Frequency f1 f0 Input Frequency f1 f0 t t
Figure 14. Time Response of the PLL/ Characteristic equation solutions (with complex solutions)
PLL Frequency f1 f0 Input Frequency f1 f0 t t
Table 3
B\A 0 1 2 3 4 5 6 7
Valid Time Constants Examples
0 YYYY YYYY NYYY NNNY NNNN NNNN NNNN NNNN 1 YYYY YYYY YYYY YYYY NYYY(1) NNNY NNNN NNNN 2 YYYY YYYY YYYY YYYY YYYY YYYY NYYY NNNY 3 YYYN YYYN YYYN YYYN YYYN YYYN YYYN YYYN 4 YNNN YNNN YNNN YNNN YNNN YNNN YNNN YNNN 5 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN 6 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
Note : Case of A[2:0] = 1 (001) and B[2:0] = 4 (100): LD[6:1] Valid Time Constants
8 N
16 Y
24 Y
32 Y
Table meaning: N = No possible capture - No stability, Y = PLL can lock.
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Figure 15.
GND Separate path for digitlal GND 1k
R2 R3
Beam current inputs VDD +5V 1k 1k
C16 R4
47F
100pF 2.2k 22F
R1 C11 C12
100pF
C14 C14
1nF
C8
1 FILTER 2 AGND 3 SDA 4 SCL 5 HS 6 VS 7 HFLY
L2
TEST28 ADCREF 27 RCI26 GCI25 BCI24 AVdd23 OVdd22 FBLK21 BOUT20 GOUT19 ROUT18 PWM517 PWM416 PWM315
C9 C10
100nF 100nF 100pF
C15 L3
13 - APPLICATION DIAGRAM
I2C bus
100H
100H
Horizontal sync Vertival sync Fly back pulse Active video
8 AV
L1
100H
10 DVss/OVss 11 XTi 12 XTO 13 PWM1 14 PWM2
100nF
9 DVdd
C1 C3 C4
C2
Xtal 8 Mhz 22pF
C5 C6 22pF
100pF 100pF 100pF 100pF
100nF
10k
R5 R6 R8
10k
R8
10k
10k
4.7F
4.7F
4.7F
4.7F
STV9432TAP
PWM outputs
PWM outputs
RGB outputs
Fast blanking ouput
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PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions A a1 b b1 C c1 D E e e3 F L S
Min. 0.1 0.35 0.23
Millimeters Typ.
Max. 2.65 0.3 0.49 0.32 45
Min. 0.004 0.014 0.009
Inches Typ.
Max. 0.104 0.012 0.019 0.013
0.5 17.7 10 1.27 16.51 7.4 0.4 7.6 1.27 8 (Max.) 0.291 0.016 18.1 10.65 0.697 0.394
0.020 0.713 0.419 0.050 0.65 0.299 0.050
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STV9432TAP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com
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